1. Field of the Invention
The present invention generally relates to a nonvolatile ferroelectric memory device more particularly, to a nonvolatile ferroelectric memory device configured to reduce the area of the device and improve the driving speed by seperating wordline/plateline decoders.
2. Description of the Background Art
Generally, a ferroelectric randaom access memory (hereinafter, referred to as xe2x80x98FRAMxe2x80x99) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a DRAM and conserves data even after the power is turned off.
The FRAM includes capacitors similar to the DRAM, but the capacitors are made of a ferroelectric substance for utilizing the characteristic of a high residual polarization of the ferroelectric substance in which data is not removed even after eliminating an electric field applied thereto.
FIG. 1 is a characteristic curve illustrating a hysteresis loop of a general ferroelectric substance.
As shown in FIG. 1, a polarization induced by an electric field does not vanish but keeps some strength (xe2x80x98dxe2x80x99 or xe2x80x98axe2x80x99 state) due to existence of a residual (or spontaneous) polarization even after the electric field is cleared.
These xe2x80x98dxe2x80x99 and xe2x80x98axe2x80x99 states may be assigned to binary values of xe2x80x981xe2x80x99 and xe2x80x980xe2x80x99 for use as a memory cell.
FIG. 2 is a structural diagram illustrating a unit cell of the FRAM device.
As shown in FIG. 2, the unit cell of the conventional FRAM is provided with a bitline BL arranged in one direction and a wordline WL arranged in another direction vertical to the bitline BL. A plateline PL is arranged parallel to the wordline and spaced at a predetermined interval. The unit cell is also provided with a transistor T1 having a gate connected to an adjacent wordline WL and a source connected to an adjacent bitline BL, and a ferroelectric capacitor FC1 having the first terminal of the two terminals connected to the drain terminal of the transistor T1 and the second terminal of the two terminals connected to the plateline PL.
The data input/output operation of the conventional FRAM is now described as follows.
FIG. 3a is a timing diagram illustrating a write mode of the FRAM.
Referring to FIG. 3a, when a chip enable signal CEB applied externally transits from a high to low level, and then address is decoded, a corresponding wordline WL is enabled. In other words, a potential of the wordline WL transits from a low to high level, thereby selecting the cell. SEN is a sense amplifier enable signal.
While the wordline WL is maintained at a high level, a high level signal of a predetermined interval and a low level signal of a predetermined signal are applied to a corresponding plateline PL.
In order to write a logic value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d in the selected cell, a data signal DIN of high or low level is applied to a corresponding bitline BL.
In other words, if a high level signal is applied to a bitline BL, and a low level signal is applied to a plateline PL in an interval where a high level signal is applied to a wordline WL, a logic value xe2x80x9c1xe2x80x9d is written in the ferroelectric capacitor FC1.
If a low level signal is applied to a bitline BL, and a high level signal is applied to a plateline PL, a logic value xe2x80x9c0xe2x80x9d is written in the ferroelectric capacitor FC1.
FIG. 3b is a timing diagram illustrating a read operation of the conventional nonvolatile ferroelectric memory device.
Referring to FIG. 3b, when a chip enable signal CEB externally transits from a high to low level, all bitlines are equalized to a low level by an equalization signal.
After each bitline is activated, an address is decoded and a corresponding wordline WL is enabled by the decoded address. As a result, a potential of the wordline WL is transited from a low to high level, thereby selecting a corresponding unit cell.
A high signal is applied to a plateline of the selected cell to destroy a data corresponding to the logic value xe2x80x9c1xe2x80x9d stored in the FRAM.
If the logic value xe2x80x9c0xe2x80x9d is stored in the FRAM, a corresponding data will not be destroyed.
The destroyed and non-destroyed data output different values, respectively, according to the above-described hysteresis loop characteristics. As a result, a sense amplifier senses logic values xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
In other words, as shown in the hysteresis loop of FIG. 1, the state moves from xe2x80x98dxe2x80x99 to xe2x80x98fxe2x80x99 when the data is destroyed while the state moves from xe2x80x98axe2x80x99 to xe2x80x98fxe2x80x99 when the data is not destroyed.
As a result, a sense amplifier enable signal SEN is activated after a predetermined time to enable the sense amplifier. Then, when the data is destroyed, the sense amplifier amplifies the data to output a logic value xe2x80x9c0xe2x80x9d. DOUT refers to output data.
After the data is outputted from the sense amplifier, the data should be recovered into the original data. Accordingly, when a high signal is applied to the corresponding wordline WL, the plateline PL is disabled from xe2x80x9chighxe2x80x9d to xe2x80x9clowxe2x80x9d.
As the storage capacity is increased, many peripheral circuits are required to embody a ferroelectric memory device. The above-described conventional nonvolatile ferroelectric memory device has a problem that the area is increased.
Accordingly, It is an object of the present invention to provide a ferroelectric memory device configured to reduce the area by separately disposing wordline/plateline decoders outside of a cell array block, and to improve the driving speed by driving each decoder separately.
It is the other object of the present invention to provide a ferroelectric memory device configured to reduce the area of wordline/plateline drivers by disposing each signal line in different layers.
It is another object of the present invention to provide a ferroelectric memory device configured to stabilize the state of an initial cell storage node.
In order to achieve the above-described objects, there is provided a nonvolatile ferroelectric memory device comprising:
a plurality of cell array blocks configured to include a plurality of ferroelectric memory cells;
a control circuit block having control circuits for reading/storing data from/to the ferroelectric memory cell;
a data bus configured to be disposed between the plurality of cell array blocks vertical to the control circuit block and to transmit data between the ferroelectric memory cell and the control circuit block;
a wordline decoder configured to select a wordline connected to the ferroelectric memory cell of the cell array block; and
a plateline decoder configured to select a plateline connected to the ferroelectric memory cell of the cell array block,
wherein the wordline decoder includes a plurality of first sub-wordline decoders and a plurality of second sub-wordline decoders disposed outside of each cell array block,
wherein the plateline decoder includes a plurality of first sub-plateline decoders and a plurality of second sub-plateline decoders disposed outside of each cell array block.
There is also provided a nonvolatile ferroelectric memory device comprising:
a plurality of cell array blocks configured to include a plurality of ferroelectric memory cells;
a control circuit block having control circuits for storing data in the ferroelectric memory cell and reading the stored data;
a data bus configured to be disposed between the plurality of cell array blocks vertical to the control circuit block and transmit data between the ferroelectric memory cell and the control circuit block;
a wordline decoder configured to select a wordline connected to the ferroelectric memory cell of the cell array block; and
a plateline decoder configured to select a plateline connected to the ferroelectric memory cell of the cell array block,
wherein the wordline decoder comprises: a plurality of first sub-wordline decoders disposed in a direction corresponding to the data bus of each cell array block; and a second sub-wordline decoder shared by the plurality of cell array blocks and disposed in a direction vertical to the data bus,
wherein the plateline decoder comprises a first sub-plateline decoder disposed in a direction corresponding to the data bus of each cell array block; and a second sub-plateline decoder shared by the plurality of cell array blocks and disposed in a direction vertical to the data bus.
There is also provided a nonvolatile ferroelectric memory device comprising:
a plurality of cell array blocks configured to include a plurality of ferroelectric memory cells; and
a control circuit block including an address control circuit for storing data in the ferroelectric memory cell and reading the stored data,
wherein the address control circuit comprises:
an address buffer for buffering an address pad signal inputted through an address pad in response to a clock enable signal;
an address latch for latching an output signal from the address buffer in response to an operation control signal; and
an address transition detecting means for detecting a transition point of an output signal from the address latch in response to a clock enable signal.